CGC=0, PCS=000, INUSE=0, PR=0
PCC CLKCFG Register
PCS | Peripheral Clock Source Select 0 (000): Clock is off (or test clock is enabled). 1 (1): OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk). 2 (2): SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz). 3 (3): SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz). 6 (6): SCGPCLK System PLL clock (scg_spll_slow_clk). |
INUSE | Clock Gate Control 0 (0): Another core is not using this peripheral. 1 (1): Another core is using this peripheral. Software cannot modify the existing clocking configuration. |
CGC | Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
PR | Enable 0 (0): Peripheral is not present. 1 (1): Peripheral is present. |